Application of carbon nano-tubes to the interconnects of a large scale integrated circuit (LSI) is taken as an example of their application to electronics. Carbon nano-tubes range from a few to tens of nanometers (nm) in diameter, and are as long as a few nanometers in length. Because of their one-dimensional electronic properties due to this shape anisotropy, the carbon nano-tube characteristically has a maximum current density allowing the flowing of current without disconnection of about 1,000,000 amperes (A) per square centimeter, which is 100 times or more as high as that of a copper interconnect. Further, with respect to heat conduction, the carbon nano-tube is ten times as high in conductivity as copper. In terms of electric resistance, it has been reported that transportation without scattering due to impurities or lattice vibration (phonon), or so-called “ballistic electron transportation,” can be realized with respect to electrons flowing through the carbon nano-tube. It is known that resistance per carbon nano-tube in this case is about 6.45 kΩ. The carbon nano-tube ranges widely from about 0.4 to about 100 nm in diameter, and its diameter is formed in a self-organizing manner. Therefore, the carbon nano-tube is characterized by an extremely limited fluctuation along its length. Because of these characteristics, a highly reliable, extremely fine metal interconnect with less migration, which is a failure mode due to high current densities, is expected to be realized in the case of applying the carbon nano-tube to an LSI interconnect.
Well-known methods of growing a carbon nano-tube include arc discharge, laser ablation (laser vaporization), chemical vapor deposition (CVD), and silicon carbide (SiC) sublimation. According to these methods, transition metal is known to be employed as catalyst metal in forming a carbon nano-tube. According to CVD and SiC sublimation, a catalyst metal layer is formed, and patterning is performed on the catalyst metal layer using lithography or etching employed in semiconductor LSI. Thereby, the position of growth of the carbon nano-tubes can be controlled through these various methods.
However, selective growth of carbon nano-tubes in oxide vias still presents fabrication problems. For example, carbon nano-tubes, need a seed layer consisting of very thin metals or metal alloys to nucleate. This thin metal layer deposits both on the vias as well as on the oxide preventing selective growth of the nano-tube in the vias. Usually a process of patterning the seed layer or catalyst metal layer is additionally required, which is a disadvantage in terms of production cost and the reliability of a semiconductor. Other methods/processes used involve a two-mask lithography level to prevent forming a seed layer over the oxide, which can also be costly and lengthen the fabrication process. This two-mask process can also lead to unreliable semiconductors.